Я пишу базовую программу для реализации алгоритма сортировки по этой ссылке Сеть для N=5 с использованием алгоритма Боуза-Нельсона.
Я сравниваю два числа с помощью компонента comb.vhd, верхний объект моей программы находится в коде ниже.
У меня нет проблем, когда я компилирую с помощью Quartus, но когда я использую modelsim для моделирования RTL, вывод всегда равен 0000, независимо от того, какие входные данные.
Я думаю, что я неправильно понял использование сигналов, но я понятия не имею, где это идет не так.
Ниже приведен основной раздел моей программы, сигналы, которые я использую:
SIGNAL out0_temp, out1_temp, out3_temp, out4_temp : bit_vector (3 downto 0); --comp1(0,1),comp2(3,4)
SIGNAL out2_temp, out4_1_temp : bit_vector (3 downto 0); --comp3(2,4)
SIGNAL out2_1_temp, out3_1_temp, out1_1_temp, out4 BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
temp : bit_vector (3 downto 0); --comp4(2,3),comp5(1,4)
SIGNAL out0_1_temp, out3 BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
temp : bit_vector (3 downto 0); --comp6(0,3)
SIGNAL out0 BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
temp, out2 BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
temp, out1 BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp : bit_vector (3 downto 0); --comp7(0,2),comp8(1,3)
SIGNAL out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp : bit_vector (3 downto 0); --comp9(1,2)
Как показано в алгоритме, я использую 9 сравнений для сортировки входных данных от наибольшего к наименьшему, как показано ниже:
BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp, out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp);
out0 <= out0_2_temp;
out1 <= out1LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out2 <= out2LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out3 <= out3LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
--Comp.vhd модуль используется для сравнения 2 чисел и переключения их, если
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;